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PDF LNBK20D2 Data sheet ( Hoja de datos )
| Número de pieza | LNBK20D2 | |
| Descripción | LNB SUPPLY AND CONTROL VOLTAGE REGULATOR | |
| Fabricantes | ST Microelectronics | |
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LNBK20D2
LNB SUPPLY AND CONTROL VOLTAGE
REGULATOR (PARALLEL INTERFACE)
s COMPLETE INTERFACE FOR TWO LNBs
REMOTE SUPPLY AND CONTROL
s GUARANTEED 400mA OUTPUT CURRENT
s LNB SELECTION AND STAND-BY
FUNCTION
s BUILT-IN TONE OSCILLATOR FACTORY
TRIMMED AT 22KHz
s FAST OSCILLATOR START-UP FACILITATES
™DiSEqC ENCODING
s TWO SUPPLY INPUTS FOR LOWEST
SO-20
DISSIPATION
s BYPASS FUNCTION FOR SLAVE
OPERATION
s LNB SHORT CIRCUIT PROTECTION AND
(MI) and the LNBA pin, thus leaving all LNB
DIAGNOSTIC
powering and control functions to the Master
s AUXILIARY MODULATION INPUT EXTENDS Receiver. This electronic switch is closed when
FLEXIBILITY
the device is powered and EN pin is LOW.
s CABLE LENGTH COMPENSATION
The regulator outputs can be logic controlled to be
s INTERNAL OVER TEMPERATURE
PROTECTION
13 or 18 V (typ.) by mean of the VSEL pin for
DataSheet4Ure.cmoomte controlling of LNBs. Additionally, it is
s BACKWARD CURRENT PROTECTION
possible to increment by 1V (typ.) the selected
voltage value to compensate the excess voltage
s COST-EFFECTIVE VERSION OF LNBP
drop along the coaxial cable (LLC pin HIGH).
SERIES
In order to reduce the power dissipation of the
DESCRIPTION
Intended for analog and digital satellite receivers,
the LNBK20D2 is a monolithic linear voltage
device when the lowest output voltage is selected,
the regulator has two Supply Input pins VCC1 and
VCC2. They must be powered respectively at 16V
(min) and 23V (min), and an internal switch
regulator, assembled in SO-20, specifically automatically will select the suitable supply pin
designed to provide the powering voltages and the according to the selected output voltage. If
interfacing signals to the LNB downconverter adequate heatsink is provided and higher power
situated in the antenna via the coaxial cable. It has
the same functionality of the LNBP1X and
losses are acceptable, both supply pins can be
powered by the same 23V source without
LNBP20 series, at a reduced output current affecting any other circuit performance.
capability. Since most satellite receivers have two The ENT (Tone Enable) pin activates the internal
antenna ports, the output voltage of the regulator
is available at one of two logic-selectable output
pins (LNBA, LNBB). When the IC is powered and
put in Stand-by (EN pin LOW), both regulator
outputs are disabled to allow the antenna
oscillator so that the DC output is modulated by a
±0.3 V, 22KHz (typ.) square wave. This internal
oscillator is factory trimmed within a tolerance of
±2KHz, thus no further adjustments neither
external components are required.
downconverters to be supplied/controlled by
others satellite receivers sharing the same coaxial
lines. In this occurrence the device will limit at 3
mA (max) the backward current that could flow
from LNBA and LNBB output pins to GND.
A burst coding of the 22KHz tone can be
accomplished thanks to the fast response of the
ENT input and the prompt oscillator start-up. This
™helps designers who want to implement the
DiSEqC protocols (*).
For slave operation in single dish, dual receiver In order to improve design flexibility and to allow
systems, the bypass function is implemented by implementation of newcoming LNB remote control
an electronic switch between the Master Input pin standards, an analogic modulation input pin is
July 2003
1/14
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LNBK20D2
ELECTRICAL CHARACTERISTICS FOR LNBK SERIES (TJ = 0 to 85°C, CI = 0.22µF, CO =0.1µF,
EN=H, ENT=L, LLC=L, VIN1=16V, VIN2=23V IOUT=50mA, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
VIN1 VCC1 Supply Voltage
VIN2 VCC2 Supply Voltage
VO1 Output Voltage
VO2 Output Voltage
∆VO Line Regulation
∆VO Load Regulation
SVR Supply Voltage Rejection
IMAX
tOFF
tON
fTONE
ATONE
DTONE
tr, tf
GEXTM
VEXTM
ZEXTM
VSW
VOL
IOZ
VIL
VIH
IIH
ICC
Output Current Limiting
Dynamic Overload
protection OFF Time
Dynamic Overload
protection ON Time
Tone Frequency
Tone Amplitude
Tone Duty Cycle
Tone Rise and Fall Time
External Modulation Gain
External Modulation Input
Voltage
External Modulation
Impedance
Bypass Switch Voltage
Drop (MI to LNBA)
Overload Flag Pin Logic
LOW
Overload Flag Pin OFF
State Leakage Current
Control Input Pin Logic
LOW
Control Input Pin Logic
HIGH
Control Pins Input Current
Supply Current
IOBK Output Backward Current
TSHDN Temperature Shutdown
Threshold
IO = 400 mA ENT=H, VSEL=L, LLC=L
IO = 400 mA ENT=H, VSEL=L, LLC=H
IO = 400 mA ENT=H, VSEL=L, LLC=L
IO = 400 mA VSEL=L, LLC=H
IO = 400 mA VSEL=L, LLC=L
IO = 400 mA ENT=H, VSEL=L, LLC=H
IO = 400 mA VSEL=L, LLC=L
IO = 400 mA ENT=H, VSEL=L, LLC=H
VIN1=15 to 18V VOUT=13V
VIN2=22 to 25V VOUT=18V
VIN1=VIN2=22V VOUT=13 or 18V
IO = 0 to 3A
VIN1 = VIN2 = 23 ± 0.5Vac fac = 120 Hz,
Output Shorted CEXT =4.7µF
Output Shorted CEXT =4.7µF
ENT=H
ENT=H
ENT=H DataSheet4U.com
ENT=H
∆VOUT/∆VEXTM,
AC Coupling
f = 10Hz to 40KHz
f = 10Hz to 40KHz
EN=L, ISW=300mA, VCC2-VMI=4V
IOL=8mA
VOH = 6V
VIH = 5V
Output Disabled (EN=L)
ENT=H, IOUT=500mA
EN=L
VLNBA = VLNBB = 18V
VIN1 = VIN2 = 22V or floating
15 27 V
16 27 V
22 27 V
23 27 V
17.3 18 18.7
V
19 V
12.5 13 13.5
V
14 V
5 50 mV
5 50 mV
65 150 mV
45
500 650 800
1100
dB
mA
ms
tOFF/15
20
0.55
40
5
22
0.72
50
10
5
24
0.9
60
15
400
ms
KHz
Vpp
%
µs
mVpp
400 Ω
0.35 0.6
V
0.28 0.5
V
10 µA
0.8 V
2.5 V
20 µA
0.3 1 mA
3.1 6 mA
0.2 3 mA
150 °C
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LNBK20D2
THERMAL DESIGN NOTE
During normal operation, this device dissipates some power. At maximum rated output current (400mA),
the voltage drop on the linear regulator lead to a total dissipated power that is of about 2W. The heat
generated requires a suitable heatsink to keep the junction temperature below the over temperature
protection threshold. Assuming a 40°C temperature inside the Set-Top-Box case, the total Rthj-amb has
to be less than 43°C/W.
While this can be easily achieved using a through-hole power package that can be attached to a small
heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB
solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous
copper area of the GND layer to dissipate the heat coming from the IC body.
The SO-20 package of this IC has 4 GND pins that are not just intended for electrical GND connection, but
also to provide a low thermal resistance path between the silicon chip and the PCB heatsink. Given an
Rthj-c equal to 15°C/W, a maximum of 28°C/W are left to the PCB heatsink. This figure is achieved if a
minimum of 25cm2 copper area is placed just below the IC body. This area can be the inner GND layer of
a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the
IC is placed. In both cases, the thermal path between the IC GND pins and the dissipating copper area
must exhibit a low thermal resistance.
In figure 4, it is shown a suggested layout for the SO-20 package with a dual layer PCB, where the IC
Ground pins and the square dissipating area are thermally connected through 32 vias holes, filled by
solder. This arrangement, when L=50mm, achieves an Rthc-a of about 28°C/W.
Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground pins
approximately in the middle of the dissipating area; to provide as many vias as possible; to design a
dissipating area having a shape as square as possible and not interrupted by other copper traces.
SO-20 SUGGESTED PCB HEATSINK LAYOUT
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| PDF Descargar | [ Datasheet LNBK20D2.PDF ] | |
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