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PDF NTB52N10 Data sheet ( Hoja de datos )
| Número de pieza | NTB52N10 | |
| Descripción | N-Channel Enhancement-Mode D2PAK | |
| Fabricantes | ON Semiconductor | |
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NTB52N10
Power MOSFET
52 Amps, 100 Volts
N−Channel Enhancement−Mode D2PAK
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
• Mounting Information Provided for the D2PAK Package
• Pb−Free Packages are Available
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Drain−to−Source Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Pulsed (Note 1)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
100
100
"20
"40
52
40
156
178
1.43
2.0
Vdc
Vdc
Vdc
Adc
W
W/°C
W
Operating and Storage Temperature Range
TJ, Tstg −55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL(pk) = 40 A, L = 1.0 mH, RG = 25 W)
EAS 800 mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 2)
RqJC
RqJA
RqJA
°C/W
0.7
62.5
50
Maximum Lead Temperature for Soldering
Purposes, 1/8in from case for 10 seconds
TL 260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu. Area 0.412 in2).
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 3
1
http://onsemi.com
VDSS
100 V
RDS(ON) TYP
30 mW @ 10 V
ID MAX
52 A
N−Channel
D
G
4
12
3
D2PAK
CASE 418B
STYLE 2
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
NTB
52N10G
AYWW
12 3
Gate Drain Source
NTB52N10
A
Y
WW
G
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NTB52N10
NTB52N10G
Package
D2PAK
D2PAK
(Pb−Free)
Shipping†
50 Units / Rail
50 Units / Rail
NTB52N10T4
NTB52N10T4G
D2PAK
D2PAK
(Pb−Free)
800 / Tape & Reel
800 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTB52N10/D
1 page  
NTB52N10
20
18
16
VDS
14
12
QT
100
80
60
10
8 Q1
6
Q2
VGS 40
4 20
2
ID = 52 A
TJ = 25°C
00
0 10 20 30 40 50 60 70
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
100
VDD = 80 V
ID = 52 A
VGS = 10 V
10
td(off)
tf
tr
td(on)
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
60
50
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.25 0.35 0.45 0.55 0.65 0.75 0.85
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.95
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
http://onsemi.com
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