PDF LT1161CS Data sheet ( Hoja de datos )

Número de pieza	LT1161CS
Descripción	Quad Protected High-Side MOSFET Driver
Fabricantes	Linear Technology
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No Preview Available ! FEATURES s Fully Enhances N-Channel MOSFET Switches s 8V to 48V Power Supply Range s Protected from – 15V to 60V Supply Transients s Individual Short-Circuit Protection s Individual Automatic Restart Timers s Programmable Current Limit, Delay Time, and Auto-Restart Period s Voltage-Limited Gate Drive s Defaults to OFF State with Open Input s Flowthrough Input to Output Pinout s Available in 20-Lead DIP or SOL Package U APPLICATIONS s Industrial Control s Avionics Systems s Automotive Switches s Stepper Motor and DC Motor Control s Electronic Circuit Breaker LT1161 Quad Protected High-Side MOSFET Driver DESCRIPTION The LT1161 is a quad high-side gate driver allowing the use of low cost N-channel power MOSFETs for high-side switching applications. It has four independent switch channels, each containing a completely self-contained charge pump to fully enhance an N-channel MOSFET switch with no external components. Also included in each switch channel is a drain sense comparator that is used to sense switch current. When a preset current level is exceeded, the switch is turned off. The switch remains off for a period of time set by an external timing capacitor and then automatically attempts to restart. If the fault is still present, this cycle repeats until the fault is removed, thus protecting the MOSFET. The LT1161 has been specifically designed for harsh operating environments such as industrial, avionics, and automotive applications where poor supply regulation and/or transients may be present. The device will not sustain damage from supply voltages of –15V to 60V. TYPICAL APPLICATION 24V CT 0.1µF V+ T1 V+ DS1 0.1µF T2 G1 0.1µF T3 DS2 0.1µF T4 LT1161 G2 INPUTS IN1 IN2 IN3 IN4 GND DS3 G3 DS4 GND G4 RS 0.01Ω IRFZ34 0.01Ω IRFZ34 0.01Ω IRFZ34 0.01Ω IRFZ34 + 50µF 50V LOAD #1 LOAD #2 LOAD #3 LOAD #4 1161 F01 Figure 1. Protected Quad High-Side Switch Switch Drop vs Load Current 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 1 2 345 LOAD CURRENT (A) 1161 TA01 1 1 page U OPERATIO (Each Channel, Refer to Functional Diagram) LT1161 The LT1161 gate pin has two states, OFF and ON. In the OFF state it is held low, while in the ON state it is pumped to 12V above supply by a self-contained 750kHz charge pump. The OFF state is activated when either the input pin is below 1.4V or the timer pin is below 3V. Conversely, for the ON state to be activated, both the input and timer pins must be above their thresholds. When the MOSFET gate voltage is less than 1.4V, the timer pin is released. The 14µA current source then slowly charges the timing capacitor back to 3V where the charge pump again starts to drive the gate pin high. If a fault still exists, such as a short circuit, the sense comparator threshold will again be exceeded and the timer cycle will repeat until the fault is removed (see Figure 2). If left open, the input pin is held low by a 75k resistor, while the timer pin is held a diode drop above 3V by a 14µA pull- up current source. Thus the timer pin automatically re- verts to the ON state, subject to the input also being high. The input has approximately 200mV of hysteresis. The sense pin normally connects to the drain of the power MOSFET, which returns through a low valued drain sense resistor to supply. When the gate is ON and the MOSFET drain current exceeds the level required to generate a 65mV drop across the drain sense resistor, the sense comparator activates a pull-down NPN which rapidly pulls the timer pin below 3V. This in turn causes the timer comparator to override the input pin and activate the gate pin OFF state, thus protecting the power MOSFET. In order for the sense comparator to accurately sense MOSFET drain current, the LT1161 supply pins must be connected directly to the positive side of the drain sense resistors. INPUT OFF NORMAL OVERCURRENT 12V V+ GATE 0V 3V TIMER 0V Figure 2. Timing Diagram NORMAL 1161 F02 APPLICATIONS INFORMATION Input/Supply Sequencing There are no input/supply sequencing requirements for the LT1161. The input may be taken up to 15V with the supply at 0V. When the supply is turned on with an input high, the MOSFET turn-on will be inhibited until the timing capacitor charges to 3V (i.e., for one restart cycle). The two V+ pins (11, 20) must always be connected to each other. Isolating the Inputs Operation in harsh environments may require isolation to prevent ground transients from damaging control logic. The LT1161 easily interfaces to low cost opto-isolators. The network shown in Figure 3 ensures that the input will be pulled above 2V, but not exceed the absolute maximum rating, for supply voltages of 12V to 48V over the entire temperature range. In order to maintain the OFF state, the opto must have less than 20µA of dark current (leakage) hot. 12V TO 48V LOGIC 2k 1/4 NEC PS2501-4 INPUT 100k LOGIC GND IN LT1161 51k POWER GROUND GND GND 1161 F03 Figure 3. Isolating the Inputs 5 5 Page TYPICAL APPLICATIONS Protected Quad 2A Industrial Switch with Isolated Inputs and Fault Output LT1161 INPUTS NEC PS2501-4 5.1k 5.1k 5.1k 5.1k 24V 18k 5.6V 1N5994B FAULT OUTPUT 2N3904 4N28 1µF + 1µF + 1µF + 1µF + 1 GND V+ 20 2 T1 19 DS1 3 IN1 18 G1 4 T2 17 DS2 5 IN2 6 T3 16 G2 LT1161 15 DS3 7 IN3 14 G3 8 T4 13 DS4 9 IN4 12 G4 10 GND V+ 11 MM74HC266A 5.1k 0.1µF 2k 24V 0.015Ω RFD16N05 0.015Ω RFD16N05 0.015Ω RFD16N05 0.015Ω RFD16N05 + 50µF 50V 100k 100k 100k LOAD #1 LOAD #2 LOAD #3 LOAD #4 100k 1161 TA02 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 11 Page

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