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PDF AT86RF211S Data sheet ( Hoja de datos )
| Número de pieza | AT86RF211S | |
| Descripción | Transceiver | |
| Fabricantes | ATMEL Corporation | |
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Data Demodulation and Crystal Selection for the
AT86RF211S
1. Introduction
This document gives an overview of the receiver chain of the AT86RF211S and its
associated embedded features:
• Discriminator: Demodulation of the RF signal (principle, measurement/tuning of
output voltage)
• Data slicer:From analog to digital world (different modes of functioning, how to set
up the data slicer threshold)
It also emphasizes the new possibilities of the AT86RF211S
• Selection of lower cost crystal
• Data rate up to 128 kbps
• Frequency deviation wider than ±100 kHz
2. From Analog to Digital
AT86RF211S
FSK
Transceiver for
ISM Radio
Applications
Application Note
2.1 Demodulation
www.DataSheet4U.com
2.1.1 Principle
The FSK modulation used by the AT86RF211S consists in coding each bit as follows:
• “0”: transmission of an RF signal at a frequency F0
• “1”: transmission of an RF signal at a frequency F1
• The channel frequency (or carrier) is the middle frequency Fc = (F0 + F1)/2
• F1 - Fc = Fc - F0 is called the frequency deviation
The receiver therefore has the overall task to:
• Down-convert the signal at lower frequencies (for filtering purposes): 10.7 MHz
and 455 kHz
• Convert the frequencies into voltages (= discriminator)
• Make a decision to separate “0” from “1” levels (= data slicer)
Rev. 5418A–WIRE–04/05
1 page  
AT86RF211S Application Note
Figure 2-5. “External” Comparison Mode: Signal Compared to its Average Value.
Demodulator
Output
(DSIN)
+
-
DAC
Data Slicer
0 A 100K
1
+
-
Data Slicer
Threshold
B
DATAMSG
SKFILT
The value of the capacitor is a trade-off: it must be low enough to make the charging time as
short as possible, but high enough to “memorize” the level during the length of the maximum
number of similar consecutive bits. The lower the data rate, the higher the capacitor. Practical
values are:
• Data rate = 2400 bps => C = 22 nF
• Data rate = 4800 bps => C = 10 nF
• Data rate = 9600 bps => C = 4.7 nF
• Data rate ≥ 19200 bps => C = 2.2 nF
This procedure makes it impossible to receive a signal containing a DC component (= a long
sequence of “0” or “1”): the signal and data slicer thresholds become very close to one another
and the decision can no longer be made. Therefore, an adequate data encoding technique
must be used to prevent any DC component.
Manchester encoding is a popular way of preventing the existence of any DC component. It
consists in encoding the data as follows:
– Logical “0”: 01
– Logical “1”: 10
This way, a long sequence of “0s” will be transformed into a “0101010101…” sequence. A
maximum of two similar successive low or high levels can be seen.
Note: Many other DC-free data encoding techniques are possible that increase the effectiveness of
the encoding, but the principle of operation is the same.
Thanks to the new “Charge & Hold” feature of the AT86RF211S, it is possible to suppress
message encoding. A dedicated application note entitled “Benefits of Charge & Hold” refer-
ence 5420, is available that details this.
5418A–WIRE–04/05
5
5 Page 
AT86RF211S Application Note
4.1.4
Meeting Rule No. 4
One must ensure that the demodulated data can be correctly data-sliced and reshaped. If the
''external'' mode is used, the average level of the demodulated signal is the reference of the
data slicer. There is no problem for meeting rule 4.
If the ''external'' mode is used in combination with the ''Charge & Hold” mode, the average
level of the demodulated signal is captured and kept as the reference of the data slicer. There
is no problem for meeting rule n°4.
If the ''internal'' mode is used, the reference level of the data slicer is the DAC output. There-
fore, you must ensure that the demodulated signal stays in the window of the data slicer
comparator.
The “internal” level can be set on the production bench, then stored in the memory of the appli-
cation module. Afterwards, the drifts to be considered and compensated for are only the drifts
of the crystals, as the discriminator offers a constant DC level over the operating temperature
range.
The LSB of the data slicer DAC is from 36 mV (at VCC = 2.4V) to 54 mV (at VCC = 3.6V). The
conversion gains of the discriminator can be expressed in mV/ppm (instead of mV/kHz) as
1 ppm is equivalent to 1 kHz in the 868/915 MHz bands. Therefore, whatever VCC, the rule is:
• NBD: 1 ppm corresponds to 0.80 × LSB
• SBD: 1 ppm corresponds to 0.40 × LSB
• MBD: 1 ppm corresponds to 0.25 × LSB
• WBD: 1 ppm corresponds to 0.15 × LSB
We recommend that the “internal” DAC level be checked and modified in accordance with the
following rule, where VPP is the DSIN peak-to-peak demodulated signal and LSB is the DAC
LSB corresponding to the current application:
• VPP < 5 × LSB: check each time the drift corresponds to 1 × LSB
• VPP < 10 × LSB: check each time the drift corresponds to 2 × LSB
• VPP = 10 × LSB: check each time the drift corresponds to 3 × LSB
The following table derives from the two afore-described rules, providing the maximum drifts
allowed between “internal” DAC corrections:
NDB
SDB
MDB
WDB
VPP < (5 × LSB)
1.5 ppm
2.5 ppm
4 ppm
6.5 ppm
VPP < (10 × LSB)
3 ppm
5 ppm
8 ppm
13 ppm
VPP > (10 × LSB)
4.5 ppm
7.5 ppm
12 ppm
20 ppm
If the current application does not exceed these limits, only the production bench setting is
mandatory. If subsequent applications do exceed these limits, a compensation will be neces-
sary (based on the temperature conditions).
5418A–WIRE–04/05
11
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