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Número de pieza LM3S6965
Descripción Microcontroller
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No Preview Available ! LM3S6965 Hoja de datos, Descripción, Manual

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PRELIMINARY
LM3S6965 Microcontroller
DATA SHEET
DS-LM3S6965-1972
Copyright © 2007 Luminary Micro, Inc.

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LM3S6965 pdf
www.datasheet4u.com
LM3S6965 Microcontroller
10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 206
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Test Modes ............................................................................................................................. 266
12.2.6 Internal Temperature Sensor .................................................................................................... 266
12.3 Initialization and Configuration ................................................................................................. 267
12.3.1 Module Initialization ................................................................................................................. 267
12.3.2 Sample Sequencer Configuration ............................................................................................. 267
12.4 Register Map .......................................................................................................................... 268
12.5 Register Descriptions .............................................................................................................. 269
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
13.4 Register Map .......................................................................................................................... 302
November 30, 2007
Preliminary
5

5 Page





LM3S6965 arduino
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LM3S6965 Microcontroller
List of Tables
Table 1.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 6-1.
Table 7-1.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Table 9-3.
Table 10-1.
Table 10-2.
Table 10-3.
Table 11-1.
Table 12-1.
Table 12-2.
Table 13-1.
Table 14-1.
Table 15-1.
Table 15-2.
Table 15-3.
Table 16-1.
Table 16-2.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 18-1.
Table 19-1.
Table 21-1.
Table 21-2.
Table 21-3.
Table 21-4.
Table 22-1.
Table 22-2.
Table 23-1.
Table 23-2.
Table 23-3.
Table 23-4.
Table 23-5.
Table 23-6.
Table 23-7.
Documentation Conventions ............................................................................................ 20
Memory Map ................................................................................................................... 43
Exception Types .............................................................................................................. 45
Interrupts ........................................................................................................................ 46
JTAG Port Pins Reset State ............................................................................................. 50
JTAG Instruction Register Commands ............................................................................... 55
System Control Register Map ........................................................................................... 65
Hibernation Module Register Map ................................................................................... 125
Flash Protection Policy Combinations ............................................................................. 141
Flash Resident Registers ............................................................................................... 142
Flash Register Map ........................................................................................................ 142
GPIO Pad Configuration Examples ................................................................................. 167
GPIO Interrupt Configuration Example ............................................................................ 167
GPIO Register Map ....................................................................................................... 168
Available CCP Pins ........................................................................................................ 205
16-Bit Timer With Prescaler Configurations ..................................................................... 208
Timers Register Map ...................................................................................................... 214
Watchdog Timer Register Map ........................................................................................ 241
Samples and FIFO Depth of Sequencers ........................................................................ 264
ADC Register Map ......................................................................................................... 268
UART Register Map ....................................................................................................... 302
SSI Register Map .......................................................................................................... 347
Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
TX & RX FIFO Organization ........................................................................................... 413
Ethernet Register Map ................................................................................................... 416
Comparator 0 Operating Modes ...................................................................................... 454
Comparator 1 Operating Modes ..................................................................................... 455
Internal Reference Voltage and ACREFCTL Field Values ................................................. 455
Analog Comparators Register Map ................................................................................. 457
PWM Register Map ........................................................................................................ 470
QEI Register Map .......................................................................................................... 505
Signals by Pin Number ................................................................................................... 519
Signals by Signal Name ................................................................................................. 523
Signals by Function, Except for GPIO ............................................................................. 528
GPIO Pins and Alternate Functions ................................................................................. 532
Temperature Characteristics ........................................................................................... 534
Thermal Characteristics ................................................................................................. 534
Maximum Ratings .......................................................................................................... 535
Recommended DC Operating Conditions ........................................................................ 535
LDO Regulator Characteristics ....................................................................................... 536
Detailed Power Specifications ........................................................................................ 537
Flash Memory Characteristics ........................................................................................ 538
Phase Locked Loop (PLL) Characteristics ....................................................................... 538
Clock Characteristics ..................................................................................................... 538
November 30, 2007
Preliminary
11

11 Page







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