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PDF ISL5827 Data sheet ( Hoja de datos )
| Número de pieza | ISL5827 | |
| Descripción | High Speed D/A Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
May 2004
ISL5827
FN6083
Dual 12-bit, +3.3V, 260+MSPS, High Speed
D/A Converter
The ISL5827 is a dual 12-bit, 260+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
This device complements the ISL5x57 and ISL5x27 families
of high speed converters, which include 8-, 10-, 12-, and
14-bit devices.
Ordering Information
PART
NUMBER
ISL5827IN
ISL5827EVAL1
TEMP.
RANGE
(°C)
PACKAGE
PKG. CLOCK
DWG. # SPEED
-40 to 85 48 Ld LQFP Q48.7x7A 260MHz
25 Evaluation Platform
260MHz
Pinout
ISL5827
(LQFP)
TOP VIEW
Features
• Low Power . . . . . 233mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• Guaranteed Gain Matching < 0.14dB
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(73dBc to Nyquist, fS = 130MSPS, fOUT = 10MHz)
• UMTS Adjacent Channel Power = 70dB at 19.2MHz
• EDGE/GSM SFDR = 90dBc at 11MHz in 20MHz Window
• Dual, 3.3V, Lower Power Replacement for AD9765
Applications
• Cellular Infrastructure - Single or Multi-Carrier: IS-136,
IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• BWA Infrastructure
• Quadrature Transmit with IF Range 0–80MHz
• Medical/Test Instrumentation and Equipment
• Wireless Communication Systems
ID5
ID4
ID3
ID2
ID1
(LSB) ID0
NC
NC
SLEEP
DVDD
AGND
ICOMP
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
QD4
QD5
QD6
QD7
QD8
QD9
QD10
QD11 (MSB)
CLK
DGND
AGND
QCOMP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL5827
www.ADabtasSohleuette4UM.caomximum Ratings
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values
TA = -40°C TO 85°C
TEST CONDITIONS
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
12 -
- Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-1.25 ±0.5 +1.25 LSB
Differential Linearity Error, DNL
(Note 8)
-1 ±0.5 +1
LSB
Offset Error, IOS
Offset Drift Coefficient
IOUTA (Note 8)
(Note 8)
-0.006
+0.006 % FSR
- 0.1
- ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-3 ±0.5 +3 % FSR
With Internal Reference (Notes 2, 8)
-3 ±0.5 +3 % FSR
Full Scale Gain Drift
With External Reference (Note 8)
- ±50
- ppm
FSR/°C
With Internal Reference (Note 8)
- ±100
- ppm
FSR/°C
Crosstalk
Gain Matching Between Channels
(DC Measurement)
fCLK = 100MSPS, fOUT = 10MHz
fCLK = 100MSPS, fOUT = 40MHz
fCLK = 260MSPS, fOUT = 40.4MHz
As a percentage of Full Scale Range
In dB Full Scale Range
- 83
-
dB
- 74
-
dB
- 73
-
dB
-1.6 0.6 +1.6 % FSR
-0.14 0.05 +0.14 dB FSR
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3)
2 20 22
-1.0 - 1.25
mA
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Rise Time
Full Scale Step
260 300
-1
-
-
MHz
ns
Output Fall Time
Full Scale Step
- 1 - ns
Output Capacitance
- 5 - pF
Output Noise
IOUTFS = 20mA
- 50
- pA/√Hz
IOUTFS = 2mA
- 30
- pA/√Hz
5
5 Page 
ISL5827
www.cDlaotsaeShtoeetht4eUc.coonmverter inputs as possible connected to the
digital ground plane (if separate grounds are used). These
termination resistors are not likely needed as long as the
digital waveform source is within a few inches of the DAC.
For pattern drivers with very high speed edge rates, it is
recommended that the user consider series termination
(50-200Ω) prior to the DAC’s inputs in order to reduce the
amount of noise.
Power Supply
Separate digital and analog power supplies are
recommended. The allowable supply range is +2.7V to
+3.6V. The recommended supply range is +3.0 to 3.6V
(nominally +3.3V) to maintain optimum SFDR. However,
operation down to +2.7V is possible with some degradation
in SFDR. Reducing the analog output current can help the
SFDR at +2.7V. The SFDR values stated in the table of
specifications were obtained with a +3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a ±40ppm/°C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
selects the reference. The internal reference can be selected
if REFLO is tied low (ground). If an external reference is
desired, then REFLO should be tied high (the analog supply
voltage) and the external reference driven into REFIO. The
full scale output current of the converter is a function of the
voltage reference used and the value of RSET. IOUT should
be within the 2mA to 22mA range, though operation below
2mA is possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V. If an external reference is used, VFSADJ
will equal the external reference. The calculation for IOUT
(Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.23V) and a 1.91kΩ RSET
resistor, then the input coding to output current will resemble
the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH
INTERNAL REFERENCE (1.23V TYP) AND
RSET = 1.91kΩ
INPUT CODE (D11-D0) IOUTA (mA)
IOUTB (mA)
1111 1111 1111
20.6
0
1000 0000 0000
10.3
10.3
0000 0000 0000
0
20.6
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -1.0V to 1.25V. ROUT (the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
VOUT = IOUT X ROUT.
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-single-
ended arrangement to achieve better harmonic rejection.
With RDIFF = 50Ω and RLOAD = 50Ω, the circuit in Figure 13
will provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the DAC is set
to 20mA (used for the electrical specifications table). Values
of RDIFF = 100Ω and RLOAD = 50Ω were used for the typical
performance curves to increase the output power and the
dynamic range. The center tap in Figure 13 must be
grounded.
In the circuit in Figure 14, the user is left with the option to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
IOUTDC x (RA//RB) V because RDIFF is DC shorted by the
transformer. If the center tap is grounded, the DC voltage is
0V. Recommended values for the circuit in Figure 14 are
RA = RB = 50Ω, RDIFF = 100Ω, assuming RLOAD = 50Ω.
The performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
allows the circuit to find a more balanced virtual ground,
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL5827.PDF ] | |
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