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PDF ISL62870 Data sheet ( Hoja de datos )
| Número de pieza | ISL62870 | |
| Descripción | PWM DC/DC Voltage Regulator Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
August 14, 2008
ISL62870
www.DataSheet4U.com
FN6708.0
PWM DC/DC Voltage Regulator Controller
The ISL62870 IC is a Single-Phase Synchronous-Buck
PWM voltage regulator featuring Intersil’s Robust Ripple
Regulator (R3) Technology™. The ISL62870 provides a low
cost solution for compact high performance applications.The
wide 3.3V to 25V input voltage range is ideal for systems
that run on battery or AC adapter power sources. Resistor
programmed output voltage setpoint and capacitor
programmed soft-start delay allow for fast and easy
implementation. Robust integrated MOSFET drivers and
Schottky bootstrap diode reduce the implementation area and
lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The PWM
frequency is 300kHz during static operation, becoming
variable during changes in load, setpoint voltage, and input
voltage when changing between battery and AC adapter
power. The modulators ability to change the PWM switching
frequency during these events in conjunction with external
loop compensation produces superior transient response.
For maximum efficiency, the converter automatically enters
diode-emulation mode (DEM) during light-load conditions
such as system standby.
Pinout
ISL62870
(16 LD 2.6X1.8 µTQFN)
TOP VIEW
GND 1
EN 2
NC 3
SREF 4
12 BOOT
11 UGATE
10 PHASE
9 OCSET
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load to 30A
• Simple Resistor Programming for Output Voltage
• ±0.75% System Accuracy: -10°C to +100°C
• Capacitor Programming for Soft-Start Delay
• Fixed 300kHz PWM Frequency in Continuous Conduction
• External Compensation Affords Optimum Control Loop
Tuning
• Automatic Diode Emulation Mode for Highest Efficiency
• Integrated High-Current MOSFET Drivers and Schottky
Boot-Strap Diode for Optimal Efficiency
• Choice of Overcurrent Detection Schemes
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Power-Good Monitor for Soft-Start and Fault Detection
• Fault Protection
- Undervoltage
- Overvoltage
- Overcurrent (DCR-Sense or Resistive-Sense Capability)
- Over-Temperature Protection
- Fault Identification by PGOOD Pull-Down Resistance
• Pb-Free (RoHS Compliant)
Applications
• Mobile PC Graphical Processing Unit VCC Rail
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Mobile PC Memory Controller Hub (GMCH) VCC Rail
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62870HRUZ
GAL
-10 to +100
16 Ld 2.6x1.8 µTQFN
L16.2.6x1.8A
ISL62870HRUZ-T*
GAL
-10 to +100
16 Ld 2.6x1.8 µTQFN
L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL62870
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All twypwicwal.DspaetaciSfihcaeteiotn4sU.com
TA = +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
POWER GOOD
PGOOD Pull-down Impedance
PGOOD Leakage Current
PGOOD Maximum Sink Current (Note 2)
GATE DRIVER
RPG_SS
RPG_UV
RPG_OV
RPG_OC
IPG
IPG_max
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5V
75 95 150 Ω
75 95 150 Ω
50 65 90 Ω
25 35 50 Ω
- 0.1 1.0 μA
- 5.0 - mA
UGATE Pull-Up Resistance (Note 2)
UGATE Source Current (Note 2)
UGATE Sink Resistance (Note 2)
UGATE Sink Current (Note 2)
LGATE Pull-Up Resistance (Note 2)
LGATE Source Current (Note 2)
LGATE Sink Resistance (Note 2)
LGATE Sink Current (Note 2)
UGATE to LGATE Deadtime
LGATE to UGATE Deadtime
PHASE
RUGPU
IUGSRC
RUGPD
IUGSNK
RLGPU
ILGSRC
RLGPD
ILGSNK
tUGFLGR
tLGFUGR
200mA Source Current
UGATE - PHASE = 2.5V
250mA Sink Current
UGATE - PHASE = 2.5V
250mA Source Current
LGATE - GND = 2.5V
250mA Sink Current
LGATE - PGND = 2.5V
UGATE falling to LGATE rising, no load
LGATE falling to UGATE rising, no load
-
1.0 1.5
Ω
- 2.0 -
A
-
1.0 1.5
Ω
- 2.0 -
A
-
1.0 1.5
Ω
- 2.0 -
A
-
0.5 0.9
Ω
- 4.0 -
A
- 21 - ns
- 21 - ns
PHASE Input Impedance
BOOTSTRAP DIODE
RPHASE
- 33 - kΩ
Forward Voltage
Reverse Leakage
CONTROL INPUTS
VF PVCC = 5V, IF = 2mA
IR VR = 25V
- 0.58 -
- 0.2 -
V
µA
EN High Threshold Voltage
EN Low Threshold Voltage
EN Input Bias Current
EN Leakage Current
PROTECTION
VENTHR
VENTHF
IEN
IENoff
EN = 5V
EN = GND
2.0 -
-V
- - 1.0 V
1.5 2.0 2.5 µA
- 0.1 1.0 µA
OCP Threshold Voltage
VOCPTH VOCSET - VO
OCP Reference Current
IOCP EN = 5.0V
OCSET Input Resistance
ROCSET EN = 5.0V
OCSET Leakage Current
IOCSET EN = GND
UVP Threshold Voltage
VUVTH VFB = %VSREF
OVP Rising Threshold Voltage
VOVRTH VFB = %VSREF
OVP Falling Threshold Voltage
VOVFTH VFB = %VSREF
OTP Rising Threshold Temperature (Note 2) TOTRTH
OTP Hysteresis (Note 2)
TOTHYS
NOTE:
2. Limits established by characterization and are not production tested.
-1.75 -
1.75 mV
9.0 10 11 µA
- 600 - kΩ
- 0 - µA
81 84 87 %
113 116 120
%
100 102 106
%
- 150 -
°C
- 25 - °C
5 FN6708.0
August 14, 2008
5 Page 
ISL62870
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
shown in Equation 13:
D
=
-V-----O---
VIN
(EQ. 13)
The output inductor peak-to-peak ripple current is written as
shown in Equation 14:
IP – P
=
-V----O-----⋅---(---1-----–----D-----)
FSW ⋅ L
(EQ. 14)
A typical step-down DC/DC converter will have an IP-P of
20% to 40% of the maximum DC output load current. The
value of IP-P is selected based upon several criteria, such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated using Equation 15:
PCOPPER
=
IL
O
A
2
D
⋅
D
C
R
(EQ. 15)
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance CO
into which ripple current IP-P can flow. Current IP-P develops a
corresponding ripple voltage VP-P across CO, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are written as Equations 16
and 17:
ΔVESR = IP – P ⋅ ESR
(EQ. 16)
and:
ΔVC = 8-----⋅---C--I--P-O----–--⋅--P-F---S----W----
(EQ. 17)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered. A capacitor dissipates heat as
a function of RMS current and frequency. Be sure that IP-P is
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at FSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitwowrw.DataSheet4U.com
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 9 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as
expressed in Equation 18:
(IM
A
2
X
⋅
(
D
–
D2
)
)
+
⎛
⎝
x
⋅
IM
A
2
X
⋅1--D--2--
⎞
⎠
IIN_RMS
=
----------------------------------------------------------------------------------------------------
IMAX
(EQ. 18)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter
Duty cycle is written as expressed in Equation 19:
D
=
----------V----O------------
VIN ⋅ EFF
(EQ. 19)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE
FIGURE 9. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. We selected the
bootstrap capacitor breakdown voltage to be at least 10V.
Although the theoretical maximum voltage of the capacitor is
PVCC - VDIODE (voltage drop across the boot diode), large
excursions below ground by the PHASE node requires that
11 FN6708.0
August 14, 2008
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL62870.PDF ] | |
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