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PDF ISL36411 Data sheet ( Hoja de datos )
| Número de pieza | ISL36411 | |
| Descripción | Quad Lane Extender | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Quad Lane Extender
ISL36411
The ISL36411 is a settable quad receive-side equalizer
with extended functionality for advanced protocols
operating with line rates up to 11.1Gbps such as
InfiniBand (QDR) and 40G Ethernet (40GBase-CR4/
SR4). The ISL36411 compensates for the frequency
dependent attenuation of copper twin-axial cables,
extending the signal reach up to at least 10m on 28AWG
cable.
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the ISL36411 can each be set to
provide optimal signal fidelity for a given media and
length. The compensation level for the filters is set by
two external control pins.
Operating on a single 1.2V power supply, the ISL36411
enables per channel throughputs of 10Gbps to 11.1Gbps
while supporting lower data rates including 8.5, 6.25, 5,
4.25, 3.125, and 2.5Gbps. The ISL36411 uses current
mode logic (CML) inputs/outputs and is packaged in a
4mmx7mm 46-lead QFN. Individual lane LOS support is
included for module applications.
Typical Application Circuit
Features
• Supports four channels with data rates up to
11.1Gbps
• Low power (~110mW per channel)
• Low latency (<500ps)
• Four equalizers in 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Equalizer boost is pin selectable
• Pin selectable equalizer boosts
• Supports 64b/66b encoded data - long run lengths
• Line silence preservation & individual lane LOS
support
• 1.2V power supply
• LOS support
Applications
• QSFP Active Copper Cable Modules
• InfiniBand QDR
• 40G Ethernet (40GBase-CR4/SR4)
• 100G Ethernet (100GBase-CR10/SR10)
• High-Speed Active Cable Assemblies
• High-Speed Printed Circuit Board (PCB) Traces
Benefits
• Thinner gauge cable
• Extends cable reach 3x
• Improved BER
Tx1[P,N]
Tx2[P,N]
Tx3[P,N]
Tx4[P,N]
1.2V
10nF
0.1µF
TDSBL
IN1[P,N]
100pF
DE VDD
OUT1[P,N]
0.1µF
IN2[P,N] OUT2[P,N]
ISL35411
0.1µF
IN3[P,N] OUT3[P,N]
0.1µF
IN4[P,N] OUT4[P,N]
DT
1.2V
Active Copper Cable Assembly
8-Pair Differential 100ΩO
Twin-Axial Cable
= 10m 28AWG
1.2V
10nF
100pF
VDD CP LOSB
0.1µF
IN1[P,N] OUT1[P,N]
0.1µF
0.1µF
0.1µF
IN2[P,N] OUT2[P,N]
Host Channel
Adapter
Rx1[P,N]
Rx2[P,N]
ISL36411
0.1µF
IN3[P,N]
0.1µF
IN4[P,N]
1.2V
DT
0.1µF
OUT3[P,N]
0.1µF
OUT4[P,N]
Rx3[P,N]
Rx4[P,N]
Fabric Switch
Connector Paddle Card
Connector Paddle Card
March 25, 2010
FN6965.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL36411
www.DataSheet4U.com
Electrical Specifications VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted. (Continued)
PARAMETERS
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Output Return Loss Limit
(Differential)
SDD22
100MHz to 4.1GHz
4.1MHz to 11.1GHz
Note 7
Note 8
dB 7
dB 8
Output Return Loss Limit
(Common Mode)
SCC22
100MHz to 2.5GHz
2.5MHz to 11.1GHz
Note 9
-3
dB 9
dB 14
Output Return Loss Limit
SDC22 100MHz to 11.1GHz
(Com. to Diff. Conversion)
-10 dB 14
Output Residual Jitter
Output Transition Time
Lane-to-Lane Skew
tr, tf
10Gbps; Up to 10m 28AWG std twin-
axial cable (~ -27dB @ 5GHz);
1200mVP-P ≤ VIN ≤ 1600mVP-P
20% to 80%
0.35
32
50
UI 6, 10,
11
ps 12
ps 14
Propagation Delay
From IN[k] to OUT[k]
500 ps 14
LOS Assert Time
Time to assert Loss-of-Signal indicator
when transitioning from active data
mode to line silence mode
50
µs 13
LOS De-Assert Time
Time to assert Loss-of-Signal indicator
when transitioning from line silence
mode to active data mode
50
µs 13
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100 µs 13
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100 µs 13
NOTES:
6. After channel loss, differential amplitudes at ISL36411 inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 4.
7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*√(f), with f in GHz. Established by characterization
and not production tested.
8. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3+13Log10(f/5.5), with f in GHz. Established by
characterization and not production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not
production tested.
10. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
11. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
12. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
13. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less. Established by characterization and not production tested.
14. Limits established by characterization and are not production tested.
5 FN6965.1
March 25, 2010
5 Page 
ISL36411
www.DataSheet4U.com
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
3/16/10
FN6965.1
page 4
• Control pin characteristics:
VOL : delete typical “0”
• Input current: max 200, typ 100
page 5
• Output res jitter: 0.35
• In Entries from Lane-to-Lane Skew all the way down, all the numbers should
move to typ column
Added High-Speed pins to ESD Ratings as follows to Abs Max Ratings:
ESD Ratings
Human Body Model
High-Speed Pins 1.5kV
All Other Pins 2kV
Removed board footprint from page 10 due to information covered in outline drawing.
2/8/10
FN6965.0 Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL36411
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6965.1
March 25, 2010
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL36411.PDF ] | |
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