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PDF SIS438DN Data sheet ( Hoja de datos )

Número de pieza SIS438DN
Descripción N-Channel MOSFET
Fabricantes Vishay 
Logotipo Vishay Logotipo



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No Preview Available ! SIS438DN Hoja de datos, Descripción, Manual

New Product
N-Channel 20-V (D-S) MOSFET
SiS438DN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
0.0095 at VGS = 10 V
20
0.0125 at VGS = 4.5 V
ID (A)a, g
16
16
Qg (Typ.)
7.3 nC
PowerPAK® 1212-8
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Gen III Power MOSFET
• 100 % Rg Tested
100 % UIS Tested
Compliant to RoHS Directive 2002/95/EC
3.30 mm
D
8D
7
D
6
D
5
S
1S
3.30 mm
2
S
3
G
4
APPLICATIONS
• DC/DC Conversion
• POL
D
G
Bottom View
Ordering Information: SiS438DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Avalanche Current
Avalanche Energy
L = 0.1 mH
Continuous Source-Drain Diode Current
TC = 25 °C
TA = 25 °C
TC = 25 °C
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
VDS
VGS
ID
IDM
IAS
EAS
IS
PD
TJ, Tstg
Limit
20
± 20
16a, g
16g
14.3b, c
11.3b, c
32g
15
11.25
16a, g
2.9b, c
27.7
17.7
3.5b, c
2.2b, c
- 55 to 150
260
Unit
V
A
mJ
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
Symbol
RthJA
RthJC
Typical
29
3.6
Maximum
36
4.5
Unit
°C/W
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 81 °C/W.
g. Package limited.
Document Number: 64826
S09-0876-Rev. A, 18-May-09
www.vishay.com
1
Free Datasheet http://www.datasheet4u.com/

1 page




SIS438DN pdf
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
45
SiS438DN
Vishay Siliconix
36
27
18 Package Limited
9
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
35 2.0
28 1.6
21 1.2
14 0.8
7 0.4
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power, Junction-to-Case
0.0
0
25 50 75 100 125
TA - Ambient Temperature (°C)
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 64826
S09-0876-Rev. A, 18-May-09
www.vishay.com
5

5 Page





SIS438DN arduino
AN822
Vishay Siliconix
105
Spreading Copper (sq. in.)
95
85
75
65
55
0%
45
100 %
50 %
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
130
120 Spreading Copper (sq. in.)
110
100
90
80
50 %
100 %
70
60 0 %
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com
4
Document Number 71681
03-Mar-06

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