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PDF ML610473 Data sheet ( Hoja de datos )
| Número de pieza | ML610473 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
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ML610471/472/473/Q471/Q472/Q473
8-bit Microcontroller with a Built-in LCD driver
FEDL610473-07
Issue Date Jan. 7, 2013
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as the UART, RC oscillation type A/D converter, and LCD driver.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version (ML610Q471/ML610Q472/ML610Q473) can rewrite programs on-board, which can contribute to reduction in
product development TAT. The flash memory incorporated into this MTP version implements the mask ROM-equivalent
low-voltage operation (1.25V or higher) and low-power consumption (typically 5uA at low-speed operation), enabling volume
production by the MTP version.
For industrial use, ML610471P/ML610472P/ML610473P/ML610Q471P/ML610Q472P/ML610Q473P with the extended
operating ambient temperature ranging from -40°C to 85°C are available.
FEATURES
• CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- Flash Memory rewrite function (MTP version only)
- Minimum instruction execution time
30.5 μs (@ 32.768 kHz system clock)
2 μs (@ 500 kHz system clock)
• Internal memory
- ML610471/ML610472/ML610473
Internal 8KByte Mask ROM (4K x 16 bits) (including unusable 256Byte TEST area)
Internal 512Byte RAM (512 x 8 bits)
- ML610Q471/ML610Q472/ML610Q473
Internal 8KByte Flash ROM (4K x 16 bits) (including unusable 256Byte TEST area)
Internal 512Byte RAM (512 x 8 bits)
• Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 12 maskable interrupt sources:
Internal source: 8 (Timer 2, Timer 3, UART0, RC Oscillation type A/D converter, TBC128Hz, TBC32Hz, TBC16Hz,
TBC2Hz)
External source: 4 (P00, P01, P02, P03)
• Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
• Watchdog timer
- Non-maskable interrupt and reset
- Free running
- Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
1 page  
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610Q471/ML610Q472/ML610Q473
VDD
VSS
RESET_N
TEST0
EPSW1−3
PSW
Timing
Controller
Flash
Writer
CPU (nX-U8/100)
GREG
0−15
ELR1−3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
ECSR1−3
DSR/CSR
PC
BUS
Controller
RESET &
TEST
RAM
512 byte
Program
Memory
(Flash)
8Kbyte
XT0
XT1
LSCLK*
VDDL
RCM*
IN1*
CS1*
RS1*
RT1*
OSC
Power
INT
1
RC-ADC
×1
Interrupt
Controller
INT
1 WDT
INT
4 TBC
Capture
×2
INT
2 8bit Timer
×2
INT
1
UART
INT
5
GPIO
Display
register
110bit
LCD
Driver
LCD
BIAS
VPP
RXD0*
TXD0*
P00 to P03
P20, P21
P35
P42 to P47
P60 to P67 (ML610Q471)
P60 to P63 (ML610Q472)
COM0 to COM4 (*1)(*2)(*3)
SEG0 to SEG13 (ML610Q471) (*1)
SEG0 to SEG17 (ML610Q472) (*2)
SEG0 to SEG21 (ML610Q473) (*3)
VL1, VL2, VL3
C1, C2
* Secondary function or Tertiary function
(*1) Select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14
segments x 2 commons with the register
(*2) Select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18
segments x 2 commons with the register
(*3) Select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22
segments x 2 commons with the register
Figure 2 ML610Q471/ML610Q472/ML610Q473 Block Diagram
5/41
5 Page 
ML610473/ML610Q473 64pin TQFP Pin Layout
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
NC
SEG17
SEG18
SEG19
SEG20
SEG21
P20
P21
P42
P43
P00
P01
P02
P03
NC(*1) / VPP(*2)
NC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MIRROR FINISH
32 NC
31 SEG4
30 SEG3
29 COM4/SEG2
28 COM3/SEG1
27 COM2/SEG0
26 COM1
25 COM0
24 VL3
23 VL2
22 VL1
21 C2
20 C1
19 NC
18 NC
17 NC
(NC): No Connection
(*1) : ML610473
(*2) : ML610Q473
Figure 8 ML610473/ML610Q473 64pin TQFP Package Pin Layout
11/41
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML610473.PDF ] | |
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