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PDF ML610Q178 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q178 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML610Q178
The low power micro controller corresponding to 5v for household appliances
I
GENERAL DESCRIPTION
FEDL610Q178FULL-01
Issue Date: May 18, 2012
Equipped with a 8-bit CPU nX-U8/100, the ML610Q178 is a high-performance 8-bit CMOS microcontroller
that integrates a wide variety of peripherals such as 10-bit A/D converter, timer, PWM, synchronous serial port,
UART, I2C bus interface (master), Battery level detect circuit, LCD driver. The nX-U8/100 CPU is capable of
executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the
3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI
mounted on the board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 μs (at 32.768kHz system clock)
Approx 0.122 μs (at 8.192MHz system clock)＠VDD = 2.2 to 5.5V
• Internal memory
− Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is
included)
− Has 4-Kbyte RAM (4096 × 8 bits) built in.
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 23 maskable interrupt sources (Internal source: 19, External source: 4)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 6ch (16-bit configuration available)
1/28
1 page  
PIN CONFIGURATION
ML610Q178 QFP package product
80pin
81pin
P20/LED0
P21/LED1
P22/LED2
P23/LED3
VSS
P90/LED4
P91/LED5
P92/LED6
P93/LED7
P67/AIN15
P66/AIN14
P65/AIN13
P64/AIN12
P63/AIN11
P62/AIN10
P61/AIN9
P60/AIN8
P47/AIN7
P46/AIN6
P45/AIN5
100pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1pin
FEDL610Q178FULL-01
ML610Q178
51pin
50pin
50 PD3/SEG19
49 PD2/SEG18
48 PD1/SEG17
47 PD0/SEG16
46 PC7/SEG15
45 PC6/SEG14
44 PC5/SEG13
43 PC4/SEG12
42 PC3/SEG11
41 PC2/SEG10
40 PC1/SEG9
39 PC0/SEG8
38 SEG7
37 SEG6
36 SEG5
35 SEG4
34 SEG3
33 SEG2
32 SEG1
31 SEG0
31pin
30pin
NC: No Connection
5/28
5 Page 
FEDL610Q178FULL-01
ML610Q178
PIN DESCRIPTION
Pin name I/O
Description
Power supply
VSS
VDD
VDDL
VPP
VL1
VL2
VL3
Test
TEST0
TEST1_N
— Negative power supply pin
— Positive power supply pin
—
Positive power supply pin for internal logic (internally generated). Connect
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS .
— Power supply pin for programming Flash ROM.
— Power supply pins for LCD bias (external input)
— Power supply pins for LCD bias (external input)
— Power supply pins for LCD bias (external input)
I/O Input/output pin for testing. Has a pull-down resistor built in.
I/O Input/output pin for testing. Has a pull-up resistor built in.
Primary/
Secondary
Logic
——
——
——
——
——
——
——
— Positive
— Negative
System
RESET_N
XT0
XT1
OSC0
OSC1
Reset input pin. When this pin is set to a “L” level, the device is placed in
I
system reset mode and the internal circuit is initialized. If after that this pin
is set to a “H” level, program execution starts. This pin has a pull-up
resistor built in.
I Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator
(see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL
O are connected across this pin and VSS as required.
I External input pin for high-speed clock. This function is allocated to the
O secondary function of the P10 pin.
— Negative
—
—
Secondary
Secondary
—
—
—
—
LSCLK
OUTCLK
O
Low-speed clock output. This function is allocated to the secondary function
of the P20/P36 pin.
Secondary
O
High-speed clock output. This function is allocated to the secondary
function of the P21 pin.
Secondary
—
—
General-purpose input port
P00 to P03
P10 to P11
I General-purpose input ports. Provided with a secondary function for each
I port. Cannot be used as ports if their secondary functions are used.
Primary Positive
General-output input port
P20 to P23
O
General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
P90 to P93
O
General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
General-purpose input/output port
P30 to P36
P40 to P47
P50 to P53
General-purpose input/output ports.Provided with a secondary function for
each port. Cannot be used as ports if their secondary functions are used.
PC0 to PC7 I/O
PD0 to PD7
PE0 to PE7
General-purpose input/output ports.Provided with a LCD segment for each
port. Cannot be used as ports if LCD segment are used.
PF0 to PF7
Primary
Primary
Primary
Positive
Positive
Positive
11/28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ML610Q178.PDF ] | |
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