PDF ML610Q173 Data sheet ( Hoja de datos )

Número de pieza	ML610Q173
Descripción	8-bit Microcontroller
Fabricantes	LAPIS Semiconductor
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No Preview Available ! ML610Q172/ML610Q173 The low power micro controller corresponding to 5v for household appliances I GENERAL DESCRIPTION FEDL610Q172-01 Issue Date: Oct 25, 2013 This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter, timer, PWM, synchronous serial port, UART, I2C bus interface (master), Battery level detect circuit, LCD driver, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The on-chip debug function that is installed enables program debugging and programming. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system:16-bit instructions − Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time Approx 30.5 μs (at 32.768kHz system clock) Approx 0.122 μs (at 8.192MHz system clock)＠VDD = 2.2 to 5.5V • Internal memory − Internal 128-Kbyte flash ROM(64K × 16-bit) − Internal 2-Kbyte Data Flash (1-Kbyte × 2) − Internal 4-Kbyte RAM (4096 × 8 -bit) (including unusable 1KByte TEST area) • Interrupt controller − 1 non-maskable interrupt sources (Internal source: 1, External source: 1) − 24 maskable interrupt sources (Internal source: 20, External source: 4)：ML610Q172 − 26 maskable interrupt sources (Internal source: 22, External source: 4)：ML610Q173 • Time base counter − Low-speed time base counter × 1 channel − High-speed time base counter × 1 channel • Watchdog timer − Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 6ch (16-bit configuration available) 1/29 1 page FEDL610Q172-01 ML610Q172/ML610Q173 Block diagram of the ML610Q173. Symbols with an asterisk “” indicate that each of them is the secondary or tertiary function of the corresponding port. VDD VSS RESET_N TEST0 TEST1_N XT0 XT1 OSC0 OSC1* LSCLK* OUTCLK* VDDL VDD VSS VREF AIN0 to AIN7＊3 CMP0P＊4 CMP0M＊4 CMP1P＊4 CMP1M＊4 CPU (nX-U8/100) Large Model EPSW1～3 PSW GREG 0～15 ELR1～3 LR ECSR1～3 DSR/CSR Timing Controller On-Chip ICE ALU Instruction Decoder EA SP Instruction Register PC BUS Controller Program Memory （Flash） 128Kbyte RESET & TEST OSC INT 1 POWER 10bit-ADC INT 1 CMP INT 2 Data-bus RAM 4096byte Interrupt Controller INT 4 TBC INT 6 8bit Timer ×6 INT WDT BLD INT 2 SSIO INT 2 UART INT 1 I2C INT 3 PWM INT 4 GPIO SCK01, SCK11 SIN01, SIN11 SOUT0, SOUT111 RXD01, RXD11 TXD01, TXD11 SDA1 SCL1 PWM41 PPWWMM5611 PW45EV0 PW45EV1 PW6EV0 PW6EV1 P00 to P03 P10 to P11 P20 to P23 P30 to P333 P36 P40 to P43 P44 to P473 P52 to P53 P80 to P852 PD0 to PD72 PF0 to PF72 1 Secondary or tertiary function 2 Select I/O port or LCD driver 3 Select I/O port or A/D converter input 4 Select I/O port or Analog comparator input LCD Driver LCD Bias COM0 to COM32 SEG0 to SEG7 SEG16 to SEG232 SEG32 to SEG39*2 VL1, VL2, VL3 5/29 5 Page FEDL610Q172-01 ML610Q172/ML610Q173 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary Logic Power supply VSS VDD VDDL VL1 VL2 VL3 Test TEST0 — Negative power supply pin — Positive power supply pin — Positive power supply pin for internal logic (internally generated). Connect capacitors (CL) (see Measuring Circuit 1) between this pin and VSS . — Power supply pins for LCD bias (external input). This function is allocated to the primary function of the P84 pin. — Power supply pins for LCD bias (external input). This function is allocated to the primary function of the P85 pin. — Power supply pins for LCD bias (external input) I/O Input/output pin for testing. This pin has a pull-down resistor built in. —— —— —— —— —— —— — Positive TEST1_N I/O Input/output pin for testing. This pin has a pull-up resistor built in. — Negative System RESET_N XT0 XT1 OSC0 OSC1 LSCLK OUTCLK Reset input pin. When this pin is set to a “L” level, the device is placed in I system reset mode and the internal circuit is initialized. If after that this pin is set to a “H” level, program execution starts. This pin has a pull-up resistor built in. — Negative I Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL O are connected across this pin and VSS as required. — — I Crystal/ceramic connection pin for high-speed clock. O A 8MHz crystal or ceramic is connected to this pin. Capacitors CDH and CGH (see measuring circuit 1) are connected across this pin and VSS. — — O Low-speed clock output. This function is allocated to the secondary function of the P20/P36 pin. Secondary — — — — — O High-speed clock output. This function is allocated to the secondary function of the P21 pin. Secondary — General-purpose input port P00 to P03 P10 to P11 I General-purpose input ports. Provided with a secondary function for each I port. Cannot be used as ports if their secondary functions are used. Primary Positive General-output input port P20 to P21 O General-purpose output ports.Provided with a secondary function for each port. Cannot be used as ports if their secondary functions are used. Primary Positive General-purpose input/output port（ML610Q172） P30 to P36 P40 to P41, P44 to P47 P50 to P51 P80 to P85 General-purpose input/output ports.Provided with a secondary function for each port. Cannot be used as ports if their secondary I/O functions are used. Primary Positive PD0 to PD7 PF0 to PF7 General-purpose input/output ports.Provided with a LCD segment for each port. Cannot be used as ports if LCD segment are used. General-purpose input/output port（ML610Q173） P30 to P33, P36 P40 to P47 P52 to P53 P80 to P85 General-purpose input/output ports.Provided with a secondary function for each port. Cannot be used as ports if their secondary I/O functions are used. Primary Positive PD0 to PD7 PF0 to PF7 General-purpose input/output ports.Provided with a LCD segment for each port. Cannot be used as ports if LCD segment are used. 11/29 11 Page

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