|
|
PDF LNBH25S Data sheet ( Hoja de datos )
| Número de pieza | LNBH25S | |
| Descripción | LNB supply and control IC | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LNBH25S (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
LNBH25S
LNB supply and control IC with step-up and I²C interface
Datasheet - production data
Features
Complete interface between LNB and I²C
bus
Built-in DC-DC converter for single 12 V
supply operation and high efficiency
(typ. 93% @ 0.5 A)
Selectable output current limit by external
resistor
Compliant with main satellite receiver output
voltage specifications (15 programmable
levels)
Accurate built-in 22 kHz tone generator suits
widely accepted standards
22 kHz tone waveform integrity guaranteed
at no-load condition
Low drop post regulator and high efficiency
step-up PWM with integrated power NMOS
allowing low power losses
LPM function (low power mode) to reduce
dissipation
Overload and overtemperature internal
protections with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
Applications
STB satellite receivers
TV satellite receivers
PC card satellite receivers
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the
LNBH25S is a monolithic voltage regulator and
interface IC, assembled in QFN24L (4x4 mm)
specifically designed to provide 13/18 V power
supply and 22 kHz tone signaling to the LNB
down-converter in the antenna dish or to the
multi-switch box. In this application field, it offers
a complete solution with extremely low
component count and low power dissipation
together with a simple design and I²C standard
interface.
Table 1: Device summary
Order code
Package
Packing
LNBH25SPQR QFN24L (4x4) Tape and reel
March 2015
DocID026736 Rev 2
This is information on a product in full production.
1/37
www.st.com
1 page  
LNBH25S
List of figures
List of figures
Figure 1: Block diagram ..............................................................................................................................6
Figure 2: Tone enable and disable timing (using external waveform) ........................................................8
Figure 3: Tone enable and disable timing (using envelope signal) ............................................................8
Figure 4: Surge protection circuit ..............................................................................................................10
Figure 5: Pin connection (top view) ..........................................................................................................13
Figure 6: DiSEqC 1.x application circuit ...................................................................................................16
Figure 7: DiSEqC 2.x application circuit ...................................................................................................17
Figure 8: Data validity on the I²C bus .......................................................................................................20
Figure 9: Timing diagram of I²C bus .........................................................................................................20
Figure 10: Acknowledge on the I²C bus....................................................................................................20
Figure 11: Example of writing procedure starting with first data address 0X2 .........................................21
Figure 12: Example of reading procedure starting with first status address 0X0 .....................................22
Figure 13: QFN24L (4x4 mm) package outline ........................................................................................34
Figure 14: QFN24L (4x4 mm) recommended footprint.............................................................................35
DocID026736 Rev 2
5/37
5 Page 
LNBH25S
Application information
2.14 IMON (minimum output current diagnostic)
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH25S is provided with a minimum output current flag by the
IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than
12 mA (typ.). IMON function should be used with the 22 kHz tone transmission deactivated,
otherwise the IMON bit could be set to “0” even if the output current is below the minimum
current threshold. To activate IMON diagnostic function, the EN_IMON I²C bit has to be set
to “1” in the data 4 register. As soon as the IMON function is active by EN_IMON=1, VOUT
rises 21 V (typ.) on the VSEL bit setting. This operation is applied to be sure that the
LNBH25S output has the higher voltage in the LNB bus. Do not use this function in an
application environment where 21 V voltage level is not supported by other peripherals
connected to the LNB bus.
2.15
PDO (overcurrent detection on output pull-down stage)
When an overcurrent occurs on the pull-down output stage due to an external voltage
source greater than the LNBH25S nominal VOUT and for a time longer than ISINK_TIME-OUT (10
ms typ.), PDO I²C bit is set to “1”. This may happen due to an external voltage source on
the LNB output (VOUT pin).
For current threshold and deglitch time details, see Table 13: "Electrical characteristics".
2.16
Power-on I²C interface reset and undervoltage lockout
The I²C interface, built into the LNBH25S, is automatically reset at power-on. As long as
the VCC is below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does
not respond to any I²C command and all data register bits are initialized to zero, therefore
the power blocks are disabled. Once VCC rises above 4.8 V typ. the I²C interface becomes
operative and data registers can be configured by the main microprocessor.
2.17
PNG (input voltage minimum detection)
When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum
thresholds, the PNG I²C bit is set to “1” and the FLT pin is set low. See Table 13: "Electrical
characteristics" for threshold details.
2.18
ISW (inductor switching current limit)
In order to allow low saturation current inductors to be used, the maximum DC-DC inductor
switching current limit threshold can be set by one I²C bit (ISW). Two values are available:
2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).
2.19
COMP (boost capacitors and inductor)
The DC-DC converter compensation loop can be optimized to properly work with both
ceramic and electrolytic capacitors (VUP pin). For this purpose, one I²C bit in the data 4
register, see COMP Table 10: "Data 4 (read/write register. Register address = 0X5)" can be
set to “1” or “0” as follows:
COMP = 0 for electrolytic capacitors
COMP = 1 for ceramic capacitors
For recommended DC-DC capacitor and inductor values see Section 5: "Typical
application circuits" and the BOM in and Table 6: "DiSEqC 2.x bill of material".
DocID026736 Rev 2
11/37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LNBH25S.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LNBH25S | LNB supply and control IC | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |