54SXXX 데이터시트 PDF ( Data sheet )

v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es 320 MH- Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Set-Up 0.25 ns Clock Skew Sp e ci f ic at ion s 66 MH- PCI CPLD and FPGA Integration Single Chip Solution 100% Resource Utilization with 100

v2.0 General-Purpose SDRAM Controller SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly increment

v5.1 SX-A Family FPGAs Leading-Edge Performance 250 MH- System Performance 350 MH- Internal Performance ™ Specifications 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I, O Pins Up to 2,012 Dedicated Flip-Flops 0.22 , 0.25 CMOS Process Technology Featu

DM54S04 DM74S04 Hex Inverting Gates DM54S04 DM74S04 Hex Inverting Gates General Description This device contains six independent gates each of which performs the logic INVERT function Connection Diagram Dual-In-Line Package June 1989 TL F 6442 1 Order Number DM54S04J DM54S04W DM74S04M or DM74S04

DM54S08 DM74S08 Quad 2-Input AND Gates DM54S08 DM74S08 Quad 2-Input AND Gates General Description This device contains four independent gates each of which performs the logic AND function Connection Diagram Dual-In-Line Package June 1989 Function Table Order Number DM54S08J DM54S08W or DM74S0