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Datasheet 74S112 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | Category |
| 1 | 74S112 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised April 2000
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
General Description
This device contains two |  Fairchild Semiconductor | flip-flop |
| 2 | 74S112 | STTL double-J-K flip-flop 54S112/74S112 STTL 型双 J－K 触发器 （负沿触发、 带清零和预置） 典型参数： f 工作频率=125MHz Pd=75mW 外引线排列图
逻辑图
功能表
输 预置
PRE
入 时钟
输 K × × × L L H H ×
出
清除
CLR
CLK
× × × ↓ ↓ ↓ ↓ H
J × × × L H L H ×
H=� |  TW | flip-flop |
74S Datasheet ( Hoja de datos ) - resultados coincidentes |
| N.º | Número de pieza | Descripción | Fabricantes | Catagory |
| 1 | 74S00 | QUAD 2-input NAND GATE ETC gate | | |
| 2 | 74S04 | HEX INVERTING GATES DM54S04 DM74S04 Hex Inverting Gates
DM54S04 DM74S04 Hex Inverting Gates
General Description
This device contains six independent gates each of which performs the logic INVERT function
Connection Diagram
Dual-In-Line Package
June 1989
TL F 6442 – 1
Order Number DM54S04J DM54S04W DM74S04M or DM74  National Semiconductor gate | | |
| 3 | 74S08 | Quad 2-Input AND Gate DM74S08 Quad 2-Input AND Gate
March 1996 Revised April 2000
DM74S08 Quad 2-Input AND Gate
General Description
This device contains four independent gates each of which performs the logic AND function.
Ordering Code:
Order Number Package Number
Package Description
DM74S08N
N14A
14-Lead Plasti Fairchild Semiconductor gate | | |
| 4 | 74S08 | Quad 2-Input AND Gates DM54S08 DM74S08 Quad 2-Input AND Gates
DM54S08 DM74S08 Quad 2-Input AND Gates
General Description
This device contains four independent gates each of which performs the logic AND function
Connection Diagram
Dual-In-Line Package
June 1989
Function Table
Order Number DM54S08J DM54S08W or DM74S0 National Semiconductor gate | | |
| 5 | 74S08 | Quadruple 2-Input Positive-AND Gates Texas Instruments gate | | |
| 6 | 74S08N | Quad 2-Input AND Gate DM74S08 Quad 2-Input AND Gate
March 1996 Revised April 2000
DM74S08 Quad 2-Input AND Gate
General Description
This device contains four independent gates each of which performs the logic AND function.
Ordering Code:
Order Number Package Number
Package Description
DM74S08N
N14A
14-Lead Plasti Fairchild Semiconductor gate | | |
| 7 | 74S10 | STTL type three 3-input NAND gate 54S10/74S10 STTL 型三 3 输入与非门 典型参数： tpd=3ns Pd=19mW/每门 线路图（1/3）
逻辑符号
逻辑式： 外引线排列图： 逻辑表：
输入 B H × L × 输出 Y L H H H
A H L × ×
C H × × L
推荐工作条件
74Ⅱ 符号 Vcc VIH VIL IOH IOL TA 参数名称 最小 TW gate | |
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