8417902XX 데이터시트 PDF ( Data sheet )

REVISIONS LTR A DESCRIPTION Add device types 03 and 04. Convert to standard military drawing format and change drawing CAGE code. Add figure 4, test circuit and switching waveforms. Inactivate device types 01 and 02 for new design. Editorial changes throughout. Update to reflect latest changes in fo

HCSL, LVCMOS Clock Generator 8413S12 DATA SHEET General Description Features The 8413S12 is a PLL-based clock generator. This high performance device is optimized to generate the processor core reference clock, the PCI-Express, sRIO, XAUI, SerDes reference clocks and the clocks for both the Gi

HCSL, LVCMOS Clock Generator 8413S12B General Description The 8413S12B is a PLL-based clock generator. This high performance device is optimized to generate the processor core reference clock, the PCI-Express, sRIO, XAUI, SerDes reference clocks and the clocks for both the Gigabit Ethernet MAC an

Clock Generator for Cavium Processors 8413S12I-100 Data Sheet General Description Features The 8413S12I-100 is a PLL-based clock generator specifically designed for Cavium Networks Octeon II processors. This high performance device is optimized to generate the processor core reference clock, the