AD712 데이터시트 PDF ( Data sheet )

FEATURES Enhanced replacement for LF412 and TL082 AC performance Settles to ±0.01% in 1.0 μs 16 V, μs minimum slew rate (AD712J) 3 MH- minimum unity-gain bandwidth (AD712J) DC performance 200 V, mV minimum open-loop gain (AD712K) Surface mount available in tape and reel in accordance with the EIA

Data Sheet 4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference AD7124-4 FEATURES 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 A typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 A typical) Full power: 23 nV rms at 9.4 SPS, gain =

Data Sheet 8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference AD7124-8 FEATURES 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 A typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 A typical) Full power: 23 nV rms at 9.4 SPS, gain =

a FEATURES Single +5 V Supply Transmit Channel On-Chip GMSK Modulator Two 10-Bit D, A Converters Analog Reconstruction Filters Power-Down Mode Receive Channel Two Sigma-Delta A, D Converters FIR Digital Filters On-Chip Offset Calibration Power-Down Mode 3 Auxiliary D, A Converters Power-Down Modes O

a FEATURES Single +5 V Supply 32-Bit Phase Accumulator On-Chip COSINE and SINE Look-Up Tables On-Chip 10-Bit DAC Frequency, Phase and Amplitude Modulation Parallel and Serial Loading Software and Hardware Power Down Options 20 MH- and 50 MH- Speed Grades 44-Pin PLCC APPLICATIONS Frequency Synthesize