SY100S891 데이터시트 PDF ( Data sheet )

5-BIT REGISTERED TRANSCEIVER SY100S891 FINAL FEATURES s s s s s s s s 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs (BUS) 1500ps max. delay from CLK2 to Receiver Outputs (Q) Individual bus enable pins

SYNCHRONOUS EQUIPMENT STRATUM 3, 3E CLOCK UNIT SY10 SY10 INTRODUCTION Date: August 30, 2002 The SY10 - an accurate time and frequency source that had been designed as a subsystem level module. The module is designed to work within ATM, SONET, SDH, and wireless systems where synchronization is v

SY10, 100EP451L 3.3V ECL 6-Bit Differential Register with Master Reset General Description The SY10, 100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All

3 Port Solenoid Valve Rubber Seal Series SY100 1 Low power consumption: 0.5 W (Standard, Without indicator light) (Current draw: 21 mA at 24 VDC) V100 Large flow type: 0.75 W (Current draw: 31 mA at 24 VDC) [Energy saving type [0.22 W] is available, too. For details, refer to catalog on page 4