TSM2N70 데이터시트 PDF ( Data sheet )

TSM2N7000 Pin assignment: 1. Gate 2. Source 3. Drain 60V N-Channel Enhancement Mode MOSFET VDS = 60V ID = 200mA RDS (on), Vgs @ 10V, Ids @ 500mA = 5.0Ω General Description The TSM2N7000 is produced using high cell density, DMOS technology. These products have been designed to minimize on-sta

TSM2N7000 60V N-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = 60V ID = 200mA RDS (on), Vgs @ 10V, Ids @ 500mA = 5.0Ω General Description The TSM2N7000 is produced using high cell density, DMOS technology. These products have been designed to minimize on-state

TSM2N7000K 60V N-Channel MOSFET TO-92 Pin Definition: 1. Source 2. Gate 3. Drain PRODUCT SUMMARY VDS (V) RDS(on)(Ω) 60 5 @ VGS = 10V 5.5 @ VGS = 5V ID (mA) 100 100 Features ● ● ● ● Low On-Resistance ESD Protection High Speed Switching Low Voltage Drive Block Diagram Ordering Informati

TSM2N7002 60V N-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = 60V RDS (on), Vgs @ 10V, Ids @ 500mA = 7.5Ω RDS (on), Vgs @ 5V, Ids @ 50mA = 13.5Ω Features Advanced trench process technology High density cell design for low on-resistance High input impedance

F-212 TSM 116 02 S DV LC (2,54mm) .100" TSM SERIES SMT .025" SQ POST HEADER TSM 118 01 T SV Mates with: SSW, SSQ, SSM, BSW, ESW, ESQ, BCS, SLW, CES, HLE, IDSS, IDSD, SMSD, SMSS SPECIFICATIONS For complete speci cations and recommended PCB layouts see www.samtec.com TSM Insulator Material