XRK4993 데이터시트 PDF ( Data sheet )

FEBRUARY 2007 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 FUNCTIONAL DESCRIPTION The XRK4993 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize

MAY 2006 PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION XRK32308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL whi

MAY 2006 PRELIMINARY XRK32309 REV. P1.0.1 LOW-COST 3.3V ZERO DELAY BUFFER GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION Offered in both 16 pin SOIC and TSSOP packages, XRK32309 is a low cost 3.3V zero delay buffer. It is designed to distribute high speed clocks by taking one reference input and dr

xr OCTOBER 2005 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 GENERAL DESCRIPTION The XRK32510 is a high performance, low jitter, low skew clock driver. The XRK32510 uses phase-lock loop (PLL) tecnology to synthesize the CLK_IN signal into 10 output signals (QA), sy