SI5317 가격 및 재고 조회

Si5317 PIN-CONTROLLED 1 711 MHZ JITTER CLEANING CLOCK Features Provides jitter attenuation for any clock Selectable output clock signal frequency format: LVPECL, LVDS, CML or One clock input , two clock outputs CMOS Input, output frequency range: Single supply: 1.8, 2.5, or 3.3 V 1 7

Si5020 SiPHY™ M ULTI -R ATE SONET, SDH C LOCK Features Complete high speed, low power, CDR solution includes the following: ! ! ! ! ! AND D ATA R ECOVERY IC Supports OC-48, 12, 3, STM-16, 4, 1, Gigabit Ethernet, and 2.7 Gbps FEC Low Power 270 mW (TYP OC-48) Small Footprint: 4 mm x 4 mm DSPLL™

Si5020C-BA Si5020 M I C R O PCB W I T H S 3 0 5 0 F O O T P R I N T Features ! Supports substitution of the Si5020 in systems designed for AMCC S3050 footprint ! Simplifies evaluation of the Si5020 device ! DSPLL™ technology eliminates external loop filter components ! Excellent jitter generati

Si5022, Si5023 PRELIMINARY DATA SHEET M ULTI -R ATE SONET, SDH CDR IC Features WITH L IMITING A MP High Speed Clock and Data Recovery device with Integrated Limiting Amp: ! ! ! ! ! Supports OC-48, 12, 3, STM-16, 4, 1, Gigabit Ethernet, and 2.7 Gbps FEC DSPLL™ Technology Low Power 370 mW (TYP)

Si5022, Si5023 PRELIMINARY DATA SHEET M ULTI -R ATE SONET, SDH CDR IC Features WITH L IMITING A MP High Speed Clock and Data Recovery device with Integrated Limiting Amp: ! ! ! ! ! Supports OC-48, 12, 3, STM-16, 4, 1, Gigabit Ethernet, and 2.7 Gbps FEC DSPLL™ Technology Low Power 370 mW (TYP)

S i 5 1 0 , 5 11 C R YS TA L O SCILLATOR (XO) 100 kH Z TO 2 5 0 M H Z Features Supports any frequency from 100 kH- to 250 MH- Low jitter operation 2 to 4 week lead times Total stability includes 10-year aging Comprehensive production test coverage includes crystal ESR and DLD On-chip