HPFC-5000 데이터시트 PDF ( Data sheet )

w w at .D w h S a ee U 4 t mAgilent HPFC-5000 Tachyon o .c Fibre Channel Interface Controller Product Brief Internal Block Diagram The Internal Block Diagram in Figure 1 below shows the high-level chip architecture for Tachyon. Inbound Message Queue Inbound Data MFS SFS Buffer Buffer Queue Qu

w w at .D w h S a ee U 4 t mAgilent HPFC-5000 Tachyon o .c Fibre Channel Interface Controller Product Brief Internal Block Diagram The Internal Block Diagram in Figure 1 below shows the high-level chip architecture for Tachyon. Inbound Message Queue Inbound Data MFS SFS Buffer Buffer Queue Qu

Tachyon TL 33 MH- PCI to Fibre Channel Controller Technical Data HPFC-5100C Features Second Generation Controller IC, Based on TACHYON Family Architecture Supports All Fibre Channel Topologies; Arbitrated Loop (FC-AL) and N_Port Fabric Attachment Supports Both Class 3 and Class 2 (via Software)

Agilent HPFC-5400 Tachyon DX2 Dual Channel Fibre Channel IC Product Overview 4K on chip boot RAM Supports fabric, point-to-point (N_Port) and loop (Public and Private) topologies Optional external boot ROM, Flash (128K Bytes) Eight full-frame inbound buffers and four full-frame outbound buffe